1. Field of the Invention
This invention relates to an analog to digital converter which converts an analog input value into a digital value, and more particularly to an analog to digital converter which can be reduced in size and effect analog to digital conversion at a high speed. The present invention further relates to an analog to digital converter which includes a plurality of comparators, and particularly to an analog to digital converter which can restrict a peak value in variation of power supply current and reduce power source noise involved in variation of the power supply current.
2. Prior Art
Analog to digital converters have been employed for a long time in an industrial field for measuring instruments such as, for example, digital voltmeters and programmable power sources. Further, in recent years, analog to digital converters have been and are employed for various public applications such as compact disk players and special applications such as CODEC for connecting a telephone set to a digital data switching network.
Further, analog to digital converters of 6 to 8 bits which can operate at a high speed of 10 to 20 MHz are used for applications of special reproduction and noise reduction in a video tape recorder for home use. As the development of the digital technology proceeds in recent years such that, for example, DRAMs (dynamic random access memories) of a comparatively large capacity are employed at a comparatively low cost, and analog to digital converters are employed widely for image processing apparatus, digital signal processors and so forth. A further higher speed operation is requested for analog to digital converters for use for the image processing apparatus, the digital signal processors and so forth.
A flash type analog to digital converter is known as an analog to digital converter which can operate at a high speed. The flash type analog to digital converter causes, when it is an n-bit flash type analog to digital converter, a total of (2.sup.n -1) comparators to operate at a time to effect analog to digital conversion. Different reference voltages obtained by division of a reference voltage using a resistor ladder wherein a total of 2.sup.n resistance elements having an equal resistance value are connected in series are inputted to the (2.sup.n -1) comparators. Accordingly, each comparator compares an analog signal voltage with a reference voltage inputted thereto. Then, the flash type analog to digital converter outputs an n-bit digital signal encoded in accordance with results of the comparison by the (2.sup.n -1) comparators. With the flash type analog to digital converter, a digital signal corresponding to an inputted analog signal voltage can be obtained at a speed much higher than integrating type analog to digital converters and successive approximation type analog to digital converters.
Further, as an analog to digital converter which can operate at a high speed, an analog to digital converter called two-step flash type analog to digital converter has been proposed in recent years and is disclosed in U.S. Pat. No. 4,533,903. The two-step flash type analog to digital converter first effects, when it is an (m+n) bit analog to digital converter, analog to digital conversion for the upper m bits using a total of (2.sup.m -1) comparators and then effects analog to digital conversion for the lower n bits using a total of (2.sup.n -1) separate comparators. Accordingly, the number of comparators employed in the two step flash type analog to digital converter totals (2.sup.m +2.sup.n -2). This is very small compared to the total number of comparators employed in such popular flash type analog to digital converters as described above.
In recent years, chopper type comparators have been and are employed as comparators for the two-step flash type analog to digital converter described above. In a chopper type comparator, an analog signal voltage is first inputted to a capacitor connected in series to the input of a CMOS (complementary metal oxide semiconductor) inverter, and then the input and the output of the CMOS inverter are short-circuited so that charge Q corresponding to the analog signal voltage is stored into the capacitor. Then, the input and the output of the CMOS inverter are opened, whereafter the capacitor to which the analog signal voltage has been inputted is connected to a reference voltage. In this instance, the CMOS inverter provides an output of a difference value between the analog signal voltage and the reference voltage in accordance with the positive or negative sign.
Another comparator for use with an analog to digital converter is disclosed in Japanese Patent Laid-Open Application No. 1-259628 wherein it includes a differential amplifier and has a correction input terminal. Comparators employing a differential amplifier are widely used in analog to digital converters together with the chopper type comparators described above. The comparator disclosed in Japanese Patent Laid-Open Application No. 1-259628 can provide an analog to digital converter which operates with a high degree of accuracy and at a high speed without being influenced by a variation of offset voltage. For example, the comparator can reduce the problem of the variation in offset voltage caused by a difference between threshold voltages a pair of transistors when MOS (metal oxide semiconductor) transistors are employed for a comparator which employs the differential amplifier.
While the flash type analog to digital converters described above are advantageous in that they can effect analog to digital conversion at a speed much higher than the integrating type analog to digital converters or the successive approximation type analog to digital converters, they have a problem in that the number of comparators involved is very great.
Also the two step flash type analog to digital converter described above has the problem that the number of comparators is still great although the number is reduced compared to the popular flash type analog to digital converters. For example, a two-step flash type analog to digital converter of 8 bits requires a total of 30 (=2.sup.4 +2.sup.4 -2) comparators. Accordingly, the conventional flash type analog to digital converters including the two-step flash type analog to digital converter are disadvantageous in that the circuit scale is great and the chip size when fabricated in an integrated circuit is large
Meanwhile, in the chopper type comparator for use with an analog to digital converter, two voltages are to be compared with each. That is, an analog input value and a reference voltage must be inputted alternately. Accordingly, the operating time for conversion is long. Further, an operation of the chopper type comparator for analog to digital conversion involves charging a capacitor in accordance with an analog input value or with a reference voltage and initialization by discharging through short circuiting. Accordingly, a problem of production of noise is also involved. The chopper type comparator has a further problem that the power dissipation is comparatively high due to the dynamic operation described just above during analog to digital conversion.
On the other hand, the comparator employing a differential amplifier normally has the operating speed of 20 to 30 MHz or so. Accordingly, the comparator cannot be employed for an analog to digital converter which effects a converting operation at a higher speed.